* ARM L2 Cache Controller

ARM cores often have a separate level 2 cache controller. There are various
implementations of the L2 cache controller with compatible programming models.
The ARM L2 cache representation in the device tree should be done as follows:

Required properties:

- compatible : should be one of:
	"arm,pl310-cache"
	"arm,l220-cache"
	"arm,l210-cache"
- cache-unified : Specifies the cache is a unified cache.
- cache-level : Should be set to 2 for a level 2 cache.
- reg : Physical base address and size of cache controller's memory mapped
  registers.

Optional properties:

- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
  read, write and setup latencies. Minimum valid values are 1. Controllers
  without setup latency control should use a value of 0.
- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
  read, write and setup latencies. Controllers without setup latency control
  should use 0. Controllers without separate read and write Tag RAM latency
  values should only use the first cell.
- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
- arm,filter-ranges : <start length> Starting address and length of window to
  filter. Addresses in the filter window are directed to the M1 port. Other
  addresses will go to the M0 port.
- interrupts : 1 combined interrupt.

Example:

L2: cache-controller {
        compatible = "arm,pl310-cache";
        reg = <0xfff12000 0x1000>;
        arm,data-latency = <1 1 1>;
        arm,tag-latency = <2 2 2>;
        arm,filter-latency = <0x80000000 0x8000000>;
        cache-unified;
        cache-level = <2>;
	interrupts = <45>;
};
