* Renesas CPG DIV6 Clock

The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
Generator (CPG). They clock input is divided by a configurable factor from 1
to 64.

Required Properties:

  - compatible: Must be one of the following
    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
    - "renesas,cpg-div6-clock" for generic DIV6 clocks
  - reg: Base address and length of the memory resource used by the DIV6 clock
  - clocks: Reference to the parent clock
  - #clock-cells: Must be 0
  - clock-output-names: The name of the clock as a free-form string


Example
-------

	sd2_clk: sd2_clk@e6150078 {
		compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
		reg = <0 0xe6150078 0 4>;
		clocks = <&pll1_div2_clk>;
		#clock-cells = <0>;
		clock-output-names = "sd2";
	};
