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#### 9.34.1 Options

The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip’s architecture reference manual.

The following table lists all available PowerPC options.

`-a32`

  Generate ELF32 or XCOFF32.

`-a64`

  Generate ELF64 or XCOFF64.

`-K PIC`

  Set EF_PPC_RELOCATABLE_LIB in ELF flags.

`-mpwrx | -mpwr2`

  Generate code for POWER/2 (RIOS2).

`-mpwr`

  Generate code for POWER (RIOS1)

`-m601`

  Generate code for PowerPC 601.

`-mppc, -mppc32, -m603, -m604`

  Generate code for PowerPC 603/604.

`-m403, -m405`

  Generate code for PowerPC 403/405.

`-m440`

  Generate code for PowerPC 440. BookE and some 405 instructions.

`-m464`

  Generate code for PowerPC 464.

`-m476`

  Generate code for PowerPC 476.

`-m7400, -m7410, -m7450, -m7455`

  Generate code for PowerPC 7400/7410/7450/7455.

`-m750cl`

  Generate code for PowerPC 750CL.

`-mppc64, -m620`

  Generate code for PowerPC 620/625/630.

`-me500, -me500x2`

  Generate code for Motorola e500 core complex.

`-me500mc`

  Generate code for Freescale e500mc core complex.

`-me500mc64`

  Generate code for Freescale e500mc64 core complex.

`-me5500`

  Generate code for Freescale e5500 core complex.

`-me6500`

  Generate code for Freescale e6500 core complex.

`-mspe`

  Generate code for Motorola SPE instructions.

`-mtitan`

  Generate code for AppliedMicro Titan core complex.

`-mppc64bridge`

  Generate code for PowerPC 64, including bridge insns.

`-mbooke`

  Generate code for 32-bit BookE.

`-ma2`

  Generate code for A2 architecture.

`-me300`

  Generate code for PowerPC e300 family.

`-maltivec`

  Generate code for processors with AltiVec instructions.

`-mvle`

  Generate code for Freescale PowerPC VLE instructions.

`-mvsx`

  Generate code for processors with Vector-Scalar (VSX) instructions.

`-mhtm`

  Generate code for processors with Hardware Transactional Memory instructions.

`-mpower4, -mpwr4`

  Generate code for Power4 architecture.

`-mpower5, -mpwr5, -mpwr5x`

  Generate code for Power5 architecture.

`-mpower6, -mpwr6`

  Generate code for Power6 architecture.

`-mpower7, -mpwr7`

  Generate code for Power7 architecture.

`-mpower8, -mpwr8`

  Generate code for Power8 architecture.

`-mcell`
`-mcell`

  Generate code for Cell Broadband Engine architecture.

`-mcom`

  Generate code Power/PowerPC common instructions.

`-many`

  Generate code for any architecture (PWR/PWRX/PPC).

`-mregnames`

  Allow symbolic names for registers.

`-mno-regnames`

  Do not allow symbolic names for registers.

`-mrelocatable`

  Support for GCC’s -mrelocatable option.

`-mrelocatable-lib`

  Support for GCC’s -mrelocatable-lib option.

`-memb`

  Set PPC_EMB bit in ELF flags.

`-mlittle, -mlittle-endian, -le`

  Generate code for a little endian machine.

`-mbig, -mbig-endian, -be`

  Generate code for a big endian machine.

`-msolaris`

  Generate code for Solaris.

`-mno-solaris`

  Do not generate code for Solaris.

`-nops=count`

  If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops.

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