HiSilicon Hip05 and Hip06 PCIe host bridge DT description

HiSilicon PCIe host controller is based on Designware PCI core.
It shares common functions with PCIe Designware core driver and inherits
common properties defined in
Documentation/devicetree/bindings/pci/designware-pci.txt.

Additional properties are described here:

Required properties
- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
- reg: Should contain rc_dbi and  either config or ecam-cfg registers
       location and length (it depends on the platform BIOS).
- reg-names: Must include
  "rc_dbi": controller configuration registers;
  and one of the following entries:
    "config": PCIe configuration space registers for non-ECAM platforms.
    "ecam-cfg": PCIe configuration space registers for ECAM platforms
- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
- port-id: Should be 0, 1, 2 or 3.

Optional properties:
- status: Either "ok" or "disabled".
- dma-coherent: Present if DMA operations are coherent.

Hip05 Example (note that Hip06 is the same except compatible):
	pcie@0xb0080000 {
		compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
		reg = <0 0xb0080000 0 0x10000>,
			  <0x220 0x00000000 0 0x2000>
			/* or <0x220 0x00100000 0 0x0f00000> for ecam-cfg*/;
		reg-names = "rc_dbi", "config" /* or "ecam-cfg" */;
		bus-range = <0  15>;
		msi-parent = <&its_pcie>;
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		dma-coherent;
		ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
		num-lanes = <8>;
		port-id = <1>;
		#interrupts-cells = <1>;
		interrupts-map-mask = <0xf800 0 0 7>;
		interrupts-map = <0x0 0 0 1 &mbigen_pcie 1 10
				  0x0 0 0 2 &mbigen_pcie 2 11
				  0x0 0 0 3 &mbigen_pcie 3 12
				  0x0 0 0 4 &mbigen_pcie 4 13>;
		status = "ok";
	};
